1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly to a level shift circuit for shifting the level of the voltage amplitude of the input signal to a different voltage amplitude.
2. Description of the Related Art
A level shift circuit changes the voltage amplitude of a signal. For example, when an output voltage of a first circuit differs from an operating range of a second circuit, a level shift circuit is arranged between the first circuit and the second circuit and the level of the signal between circuits is adjusted. For example, in the driving system for an liquid crystal display panel, signals having various voltage amplitudes that are mutually different are employed. In this case, powers with these signals having different voltage amplitudes are generated from a common power supply and a level shift circuit is provided to adjust the levels of the signals between circuit blocks having different voltage amplitudes.
One circuit configuration for the level shift circuit for changing and outputting the voltage amplitude of an input signal source is a booster circuit employing capacitors and switching transistors. Another circuit configuration may employ inverter circuits to change the input signal amplitude to the voltage amplitude of the power supply. For example, JP-A-2005-266043 discloses a level shift circuit for an image display panel. A level shift circuit employing capacitor and switching devices is mentioned. Furthermore, a level shift circuit is mentioned where CMOS (Complementary Metal Oxide Semiconductor) inverters are connected in parallel. The CMOS inverter type of level shift circuit further connects a MOS transistor in series to each inverter so as to reduce the shoot-through current.
Using the CMOS inverter type of level shift circuit disclosed in the above-mentioned document enables the power consumption to be reduced with a simple configuration. This circuit configuration is suited for circuit systems such as those employed in LCDs (Liquid Crystal Display) for low power consumption. However, in the CMOS inverter type of level shift circuit, the response speed may depend on the threshold of the transistor. For example, in a CMOS inverter type of level shift circuit, suppose the supply voltage is 5.4 V, the gate of an n-channel transistor and the gate of a p-channel transistor forming the CMOS inverter are connected in common, and the common gate inputs a signal having voltage amplitude of 2.7 V. In this case, a signal having voltage amplitude of 5.4 V is obtained from a connection point connecting the n-channel transistor and the p-channel transistor. In this manner, the input signal having the voltage amplitude of 2.7 V has its signal level shifted to the output signal having the voltage amplitude of 5.4 V. In this level shift operation, the pulse rise time and the pulse fall time of the output signal is substantially dependent on the threshold of the n-channel transistor. If the threshold of the n-channel transistor is high, these transition times are substantially delayed. When the threshold is low, the shoot-through current during a transition increases and desirable low power consumption is prevented.
An advantage of the present invention is providing a level shift circuit capable of keeping the transition time within a predetermined range and improving the driving margin.